Trench structure substantially filled with high-conductivity material

ABSTRACT

A trench structure that is substantially filled with high-conductivity material such as refractory metal particularly suitable for fast switching trench MOSFET applications. The trench is first lined by a dielectric material such as silicon dioxide. A layer of polysilicon is then formed on the dielectric material and provides buffering for stress relief. The trench is then filled substantially with refractory metal such as tungsten.

BACKGROUND OF THE INVENTION

[0001] The present invention relates in general to semiconductor devicesand processing, and in particular to trench structures used in, forexample, trench metal-oxide-semiconductor field effect transistors(MOSFETs), and methods of their manufacture.

[0002]FIG. 1 is a simplified cross section of a portion of an n-channeltrench MOSFET. A trench 10 is lined with an electrically insulatingmaterial 12, such as silicon dioxide, that acts as gate dielectric. Itis then filled with a conductive material 14, such as polysilicon, thatprovides the transistor gate terminal. The trench extends into an n-typedrain region 16 which may be electrically contacted through thesubstrate of the device. A p-type well or body region 15 is formed ontop of the substrate, and n-type source regions 18 are formed on eithersides of trench 10 as shown. The active region of the MOS transistor isthus formed in channel region 20 adjacent to gate 14 and between source18 and drain 16.

[0003] Trench transistors are often used in power-handling applications,such as power supply management circuitry, hard disk drive circuitry,etc. Trench transistors may operate at 12-100 V, as compared to 2-5 Vfor a logic-type MOSFET. The gate of a trench transistor, which isproportional to the depth of the trench, is made relatively wide toimprove the current-handling capability of the trench transistor. Thesection of the trench transistor shown in FIG. 1 is often referred to asa cell because it contains one portion of the device that is repeatedacross the die. The trenches in, for example, power MOSFETs, aretypically laid out in either a grid pattern, as shown in FIG. 2, forminga closed cell configuration, a stripe pattern 30, as shown in FIG. 3,forming an open cell configuration, or other type of patterns, such as ahexagonal pattern. With the substrate of the die acting as the commondrain terminal for the cells, all source terminals are connectedtogether and all gate terminals are connected together to form one largetrench MOSFET.

[0004] For many applications a key performance characteristic of thetrench MOSFET is its switching speed. To maximize the switching speed ofthe trench MOSFET it is desirable to minimize the resistivity of itsgate material. As the die size for larger power MOSFETs and the lengthof trenches increases, the speed at which gate charge is distributedacross the length of the trenches becomes a concern. To decrease thegate resistivity for the larger trench MOSFETs, trenches are typicallydivided into shorter segments and gate metal contact is distributedacross the surface of the die. FIG. 4 is a top view of a die showinggate and source wiring for a large trench power MOSFET of the open celltype. The gate which is typically made of metal (e.g. aluminum) includesbonding pad area 400 that receives bond wire 402, and gate buses 404that extend in parallel across the die. Gate buses 404 distribute thegate bias voltage to trenches 406, only a few of which are shown forillustrative purposes. Accordingly, instead of relying on the gatematerial inside each trench, which is typically polysilicon, topropagate the gate bias voltage, metal buses 404 ensure faster and moreuniform distribution of gate charge to the far end trenches across thedie. Thus, gate buses 404 provide a low-resistance path from gatebonding pad 402 to the active gates across the die, improving theswitching speed of the MOSFET.

[0005] The improved switching speed that is brought about by the busingof the gate electrode across the die, however, comes at the price ofincreased resistivity on the source electrode. This is because insteadof having a single contiguous metal layer blanketing the top surface ofthe die, the source metal layer must be broken into several sections 408to allow for gate busing. The higher source resistivity adverselyimpacts the MOSFET's drain-to-source on resistance R_(DSon), anotherspeed-critical performance characteristic for power MOSFETs.

[0006] It is therefore desirable to produce a trench that is filled withlow resistivity material for applications such as trench MOSFETs wherelower gate resistivity and faster switching can be obtained withoutadversely impacting R_(DSon).

SUMMARY OF THE INVENTION

[0007] The present invention provides a trench structure that issubstantially filled with refractory metal to form, for example, MOSFETgate terminals with low resistivity and fast switching speed. A trenchtransistor fabricated with the trench process according to the presentinvention exhibits lower gate resistivity for faster switching whilemaintaining low gate leakage current. The lower resistivity of the gatematerial eliminates the need for busing of the gate contact metal acrossthe top surface of the die.

[0008] This in turn allows for a single-square, contiguous sourcecontact layer for optimum R_(DSon).

[0009] In a specific implementation, after the formation of the trenchesand the gate dielectric layer, a buffer layer of, for example,polysilicon is formed over the gate dielectric layer. A refractory metalsuch as tungsten is then deposited over the buffer polysilicon layerusing, for example, tungsten hexafluoride in a low-pressurechemical-vapor deposition (LPCVD) process. The buffer polysilicon layerrelieves stress present in the gate dielectric layer and reduces gateleakage. The use of metal as the gate material reduces dopingrequirement for the buffer poly. This results in lower gate leakagecurrent for n-channel trench MOSFETs and can eliminate problemsassociated with high energy implants such as boron penetration inp-channel trench MOSFETs.

[0010] Accordingly, in one embodiment, the present invention provides atrench structure including a trench formed in a substrate, a dielectricmaterial lining at least a wall of the trench to form a dielectriclayer, a buffer layer formed on the dielectric layer, the buffer layerhaving a first conductivity, and a high-conductivity layer formedadjacent to and electrically coupled to the buffer layer, thehigh-conductivity layer having a second conductivity greater than thefirst conductivity.

[0011] In a more specific embodiment, the present invention provides atrench metal-oxide-semiconductor field effect transistor (MOSFET)including a trench formed in a silicon substrate, a gate oxide layerlining side-walls and bottom of the trench, a polysilicon buffer layerlining the gate oxide layer, and a metal layer filling a center portionof the trench.

[0012] In yet another embodiment, the present invention provides amethod for fabricating a trench structure in a substrate, the methodincluding the steps of (a) forming a trench in the substrate; (b)forming a dielectric layer to line the trench; (c) forming a layer ofbuffer material on the dielectric layer to fill a first portion of thetrench, the buffer material having a first electrical conductivity; and(d) filling a second portion of the trench with a high-conductivitymaterial having a second electrical conductivity, the second electricalconductivity being greater than the first electrical conductivity.

[0013] The following detailed description and the accompanying drawingsprovide a better understanding of the nature and advantages of therefractory metal gate trench MOSFET of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014]FIG. 1 shows a cross section of a typical trench transistor;

[0015]FIG. 2 is a simplified perspective view of a closed-cell gateconfiguration;

[0016]FIG. 3 is a simplified perspective view of an open-cell gateconfiguration;

[0017]FIG. 4 is a top view of a trench MOSFET die showing gate andsource busing on the die surface;

[0018]FIG. 5 is a simplified cross section of a portion of a trenchtransistor according to one embodiment of the present invention;

[0019] FIGS. 6A-6D illustrate cross sections of a portion of a substratebeing fabricated to produce a metal-gate trench transistor according toan embodiment of the present invention;

[0020]FIG. 7 is a simplified flow chart of a process according to thepresent invention; and

[0021]FIG. 8 is a top view of a large power MOSFET die showing the gateand source busing as enabled by the present invention.

DESCRIPTION OF THE SPECIFIC EMBODIMENTS

[0022] The present invention provides a trench structure for use in, forexample, double-diffused power transistors (DMOS) exhibiting superioroperating characteristics, specifically, faster gate switching and lowerR_(DSon). These advantages are obtained by making a trench structurewith a gate material that is made up substantially of high conductivitymaterial such as refractory metal. While the trench structure accordingto the present invention is described in the context of trench MOSFETs,it is to be understood that similar advantages can be obtained in othersemiconductor structures such as trench capacitors and the like.

[0023] Referring to FIG. 5, there is shown a simplified cross section ofa portion of an exemplary n-channel trench transistor 500 with alow-resistance gate according to one embodiment of the presentinvention. Each trench is lined with a thin layer of dielectric materialsuch as silicon dioxide (gate oxide) 502, and then filled with a bufferlayer 504 and a high-conductivity center portion 506. Buffer layer 504is preferably made up of doped polysilicon and the high-conductivitycenter portion 506 is made up of refractory metal such as tungsten. Ifthe trench undergoes a subsequent temperature cycle, a layer of tungstenpolycide (WSi_(x)) 512 will be formed at the polysilicon-tungsteninterface. It is to be understood that the term “polycide” used hereinrefers to silicide as well as polycide. A dielectric layer 508 overliesthe gate region and electrically isolates the gate from sourcemetallization layer 510. The gate is electrically coupled to a gate busor termination area 512. The high-conductivity center portion of thegate provides a low resistance path from the gate bus to the active gatearea.

[0024] A direct interface between high-conductivity layer 506 and gateoxide layer 502 may create stress in the gate oxide degrading thebreakdown strength of the gate oxide layer, and possibly increasing thegate leakage current, I_(GSS). Buffer layer 504 serves to maintain thedielectric strength of gate oxide layer 502 and promotes adhesionbetween gate oxide layer 502 and high-conductivity gate material 506,reducing peel-off. With current state of the art, buffer layer 504 mayhave a thickness of about 2,000 to 3,000 Å.

[0025] A preferred method of fabricating an exemplary n-channel metalgate trench MOSFET according to the present invention will be describedhereinafter in connection with the cross-sectional views shown in FIGS.6A-6D and the process flow diagram of FIG. 7. It is to be understoodthat the use of an n-channel transistor is for illustrative purposesonly, and that the same advantages can be obtained for a p-channelMOSFET fabricated according to the principles teachings of the presentinvention. Referring to FIG. 6A, there is shown an exemplary crosssection of a portion of a substrate 600 processed up to the formation oftrenches 602. This includes the various steps that form p-well 604,heavy body 606, source regions 608, and cell termination well 610.Further, trenches 602 have been formed in the substrate, and a thindielectric layer 612 lines the trenches. Dielectric layer 612 acts asthe gate dielectric, and is typically made of silicon dioxide but couldbe made of other dielectric material such as a nitride, or oxynitride.It is to be understood that any one of a number of known trenchprocesses, including those with different well or body structures, canbe employed for performing these or similar steps to prepare thesubstrate up to this point. An example of a preferred trench MOSFETprocess describing these steps in greater detail can be found incommonly-assigned patent application number 08/970,221, titled “FieldEffect Transistor and Method of its Manufacture,” which is herebyincorporated by reference in its entirety.

[0026] Referring to FIG. 6B, after the formation of gate dielectriclayer 612, a layer of polysilicon 614 is deposited over the substrateincluding over termination area 616 which is isolated from the substrateby a thick oxide region 618. It is understood that as used herein theterm “polysilicon” includes polysilicon and amorphous silicon.Polysilicon layer 614 is doped using conventional doping processes suchas POCL₃ for n-type poly (n-channel transistor), p-type (e.g., boron) orn-type (e.g., phosphorous) implant for p-channel or n-channeltransistors, respectively, or in-situ doping of n or p type dopants.Exemplary sizes for the various dimensions may be, for example, about 1μm for the starting width of the trenches, about 500 Å for the gateoxide thickness, and about 3000 Å for the polysilicon thickness.

[0027] Next, a layer of high-conductivity material such as metal 620, isdeposited over poly 614 as shown in FIG. 6C. The layer ofhigh-conductivity material 620 may be any type of refractory metal suchas tungsten, titanium, platinum, copper, or the like. Tungsten is usedherein for illustrative purposes. The metal formation step is performedusing preferably a low-pressure chemical vapor deposition (LPCVD)process with a fluoride-containing compound such as tungstenhexafluoride (WF₆) as a precursor. Other processes, such as physicalvapor deposition (sputtering) and sintering may be used, but LPCVDexhibits low sticking coefficient, which results in a very conformaldeposition, and reliably fills the trenches in a void-free manner.Further, it is believed that fluorine from the reaction of the precursorused in the tungsten formation migrates through polysilicon 614 andsegregates at the interface between the bulk silicon and gate oxide 612,and creates Si-F bonds that passivates the surface of the gate oxide.The Si-F bond is typically stronger than the traditional Si-H bond, andresults in a fluorinated gate dielectric layer that is more stable androbust, and less likely to leak current due to stress. The LPCVDdeposition process can be performed, for example, at between about 0.1to 0.5 Torr.

[0028]FIG. 6D is a simplified cross section of substrate 600 after thepolysilicon/tungsten etch, but before the resist strip. A layer ofphotoresist 622 has been patterned to preserve gate tungsten 620 andpolysilicon 614 over termination region 616. The etching step thatclears the tungsten and polysilicon from the field, may or may notremove some of the polysilicon and tungsten from the trenches, possiblycreating a recess 624 of the gate from the surface of the substrate. Thegates of the various cells of the trench transistor are electricallycoupled to the gate bus and gate pad by conventional methods (notshown).

[0029] The final processing after photoresist strip includesconventional steps of dielectric deposition followed by contact mask andetch, and metallization followed by metal mask and etch. Finally, thesubstrate is passivated followed by pad mask and etch and a final alloystep. Thus, the alloy step which may occur at, for example, about 400°C., is the only step that exposes the poly/tungsten interface inside thetrench to a temperature cycle. This temperature treatment causes theformation of a thin layer of tungsten-polycide (WSi_(x)) 626 at thepoly/tungsten interface. The resulting trench structure after the alloystep thus includes gate oxide 612, poly buffer 614, polycide 626 andtungsten 620.

[0030]FIG. 7 is a simplified flow chart of a process module for theformation of a metal-gate trench 700 according to an exemplaryembodiment of the present invention in the context of a trench MOSFETprocess. In the example shown, trench process module 700 is placed aslate in the process flow as possible to avoid exposing the trench tohigh temperature cycles. Thus, according to this embodiment, the stepsof forming cell termination (71), defining active areas (72), forming awell (73) and heavy body (74), and source regions (75) occur prior totrench formation. Trench process module 700 according to the presentinvention includes a step of forming trenches in the substrate (step702) followed by forming gate dielectric layer (e.g., SiO₂) on thesidewalls and bottom of the trench (step 704). Then, a layer ofpolysilicon is formed in the trench (step 706) over the gate dielectriclayer. The polysilicon may be doped using one of a variety of differentknown doping mechanisms. The trench is then filled (step 708) withhigh-conductivity material such as tungsten using preferably an LPCVDprocess. A masking step protects selected portions of the metal layerand polysilicon during an etch step (710) that removes the metal and thepolysilicon from the field of the substrate except where protected bythe etch mask. Subsequent steps typically include defining of contactareas (76), metallization and patterning (77), passivation (78) andalloy (79) and are based on known methods to complete the fabricationprocess of the trench transistor.

[0031] The processing of the metal-gate trench (700) according to thepresent invention can be viewed as an independent process module thatcan be performed at different points within the process flow of avariety of different trench MOSFET processes. For example, the exemplaryembodiment described above performs the trench process module preferablyafter the last dopant junction formation (i.e., after step 75) to avoidsubsequent high temperature cycles. This minimizes the amount ofpolycide (or silicide) that forms at the poly-tungsten interface due tothe temperature treatment and avoids undesirable thinning of the polybuffer which may otherwise contribute to increased leakage current.Minimum polycide formation also maximizes the gate conductivity.According to different embodiments of the present invention, however,the trench process module 700 may be performed before the formation ofthe source and body regions (e.g., between steps 72 and 73) or at anyother suitable point in the process flow depending on the application.

[0032] There are a number of advantages offered by the metal-gate trenchMOSFET of the present invention. With high-conductivity material such asmetal used for forming the gate, trenches can extend over long distanceswithout gate resistivity becoming a constraint. Thus, even for largertrench MOSFETs that are implemented on large dies, the metal-gate trenchMOSFET process according to the present invention eliminates the needfor segmentation of the trenches and busing of the gate metal across thedie without compromising the gate switching speed. FIG. 8 is asimplified top view of a trench transistor die 800 according to anembodiment of the present invention. Trenches 801 extend full lengthacross die 800 contacting a perimeter gate bus 802 that distributes gatecharge from gate pad 804 to the active gate regions. Thus, sourcecontact layer 806 can be a single contiguous square of metal whichprovides for much reduced R_(DSon) compared to conventional trenchtransistor die with interior gate busing.

[0033] Another advantage of the metal-gate trench process of the presentinvention is significant improvement in gate oxide reliability andintegrity. This is due to a combination of factors including thelowering of the polysilicon doping levels as allowed by the presentinvention. The higher conductivity of the gate metal allows reducing thepolysilicon doping concentration without adversely impacting gateswitching speed. For example, the resistivity of highly dopedpolysilicon is typically about 500 μΩ-cm, as compared to 0.5 μΩ-cm fortungsten, and 50 μΩ-cm for polycide (WSi₂). Thus, the polysilicon layerneed not be as highly doped as in conventional poly-gate trench MOSFETs.In the case of conventional n-channel trench MOSFETs, for example, it istypical to find POCL₃ highly doped polysilicon which is one of the majorcontributors to increased gate leakage current I_(GSS). Instead ofPOCL₃, in one embodiment, the present invention dopes the bufferpolysilicon layer by implanting, for example, phosphorous at reducedconcentrations of, for example, 1×10¹⁸. This directly results in reducedgate leakage current I_(GSS). Further, another undesirable side effectof implants in the case of conventional p-channel trench MOSFETs, forexample, is a phenomenon commonly referred to as boron penetration.Boron penetration occurs when the implanted boron penetrates through thegate oxide and into the channel region adversely affecting the MOSFETthreshold voltage. The present invention allows for the reduction of theboron doping concentration requirements to, for example, 1×10¹⁸, thusreducing the boron penetration effect. The reduced gate leakage currentfor n-channel transistors, reduced boron-penetration in the case ofp-channel transistors, as well as the stronger Si-F bonds at the Si-SiO₂interface (as described above) provide for a more robust trench MOSFETwith significantly improved gate oxide reliability and integrity.

[0034] While the above is a complete description of specific embodimentsof the present invention, various modifications, variations, andalternatives may be employed. For example, although specific embodimentsof the low-resistivity trench process module have been described in thecontext of a trench MOSFET process, the same or a similar process modulecan be employed in other processes such as those forming trenchcapacitors or other similar structures. Also, while tungsten is given asan example of a low-resistivity gate material, other materials, such astitanium silicide or platinum silicide, or other refractory metals maybe used in forming low-resistivity gate. Similarly, although polysiliconis given as an example of a gate buffer material, other materials mayprovide suitable stress relief while operating as a gate material incontact with the gate dielectric material. Further, the specificembodiment has been described in the context of silicon wafer processingfor illustrative purposes only, and other types of substrates, such as asemiconductor-on-insulator substrate, a silicon-germanium substrate, ora silicon carbide substrate, for example, could be used with. Therefore,the scope of this invention should not be limited to the embodimentsdescribed, and should instead be defined by the following claims.

What is claimed is:
 1. A trench structure comprising: a trench formed ina substrate; a dielectric material lining at least a wall of the trenchto form a dielectric layer; a buffer layer formed on the dielectriclayer, the buffer layer having a first conductivity; and ahigh-conductivity layer formed adjacent to and electrically coupled tothe buffer layer, the high-conductivity layer having a secondconductivity greater than the first conductivity.
 2. The trenchstructure of claim 1 wherein the buffer layer comprises polysilicon. 3.The trench structure of claim 2 wherein the polysilicon is at least2,000 to 3,000 Å in thickness.
 4. The trench structure of claim 2wherein the high-conductivity layer fills a center portion of the trenchand comprises metal.
 5. The trench structure of claim 4 wherein thehigh-conductivity layer comprises any one of a number of refractorymetals including tungsten, titanium, platinum, or any combinationthereof.
 6. The trench structure of claim 4 wherein the trench is formedin a silicon substrate and the dielectric material comprisessilicon-dioxide.
 7. The trench structure of claim 6 wherein thehigh-conductivity layer comprises tungsten deposited using low-pressurechemical vapor deposition processing, and wherein the trench structurefurther comprises a layer of polycide between the buffer layer and thehigh-conductivity layer.
 8. The trench structure of claim 7 furthercomprising a fluorinated interface between the dielectric layer and thewall of the trench.
 9. A trench metal-oxide-semiconductor field effecttransistor (MOSFET) comprising: a trench formed in a silicon substrate;a gate oxide layer lining side-walls and bottom of the trench; apolysilicon buffer layer lining the gate oxide layer; and a metal layerfilling a center portion of the trench.
 10. The trench MOSFET of claim 9further comprising source regions of a first conductivity type formed oneither sides of the trench and inside a body region of a secondconductivity type.
 11. The trench MOSFET of claim 10 wherein the metallayer comprises tungsten.
 12. The trench MOSFET of claim 11 wherein thetrench further comprises a layer of polycide sandwiched between thepolysilicon buffer layer and the metal layer.
 13. The trench MOSFET ofclaim 12 wherein the tungsten is formed by low pressure chemical vapordeposition processing using hexafluoride as a precursor.
 14. A trenchtransistor comprising: a trench extending into a bulk silicon portion ofa substrate; a gate oxide layer lining the trench walls and bottom; anda fluorinated interface region between the bulk silicon portion of thesubstrate and the gate oxide layer.
 15. The trench transistor of claim14 wherein the trench further comprises: a buffer polysilicon layerlining the gate oxide layer; and a metal layer filling a center portionof the trench.
 16. The trench transistor of claim 15 wherein the metallayer comprises tungsten, and wherein a layer of polycide is sandwichedbetween the metal layer and the buffer polysilicon layer.
 17. A methodfor fabricating a trench structure in a substrate, the method comprisingthe steps of: (a) forming a trench in the substrate; (b) forming adielectric layer to line the trench; (c) forming a layer of buffermaterial on the dielectric layer to fill a first portion of the trench,the buffer material having a first electrical conductivity; and (d)filling a second portion of the trench with a high-conductivity materialhaving a second electrical conductivity, the second electricalconductivity being greater than the first electrical conductivity. 18.The method of claim 17 wherein the step of forming a layer of buffermaterial comprises forming a layer of polysilicon.
 19. The method ofclaim 18 wherein the step of forming a layer of polysilicon furthercomprises a step of implanting the layer of polysilicon.
 20. The methodof claim 18 wherein the step of filling a second portion of the trenchwith a high-conductivity material comprises forming a layer ofrefractory metal such as tungsten.
 21. The method of claim 20 whereinthe step of forming a layer of refractory metal comprises a low pressurechemical vapor deposition (LPCVD) process.
 22. The method of claim 21wherein a fluoride-containing precursor is used in the LPCVD process.23. The method of claim 21 wherein the fluoride-containing precursorcomprises tungsten hexafluoride.
 24. The method of claim 20 wherein thetrench structure is formed as part of a trench transistor, and whereinthe steps forming the trench occur after steps involving formation ofdopant junctions.
 25. The method of claim 24 further comprising a stepalloy after the trench structure is formed whereby polycide is formed atan interface between the metal layer and the polysilicon buffer layer.26. A method for fabricating a trench transistor, the method comprising:(a) forming a trench in a bulk silicon region of a substrate; (b)growing a gate oxide layer to line the trench; (c) depositing aconformal layer of polysilicon on the gate oxide layer to fill a firstportion of the trench; and (d) substantially filling a remainder of thetrench with a metal layer formed in a low pressure chemical vapordeposition (LPCVD) process.
 27. The method of claim 26 wherein the stepof filling comprises depositing tungsten by the LPCVD process usingtungsten hexafluoride as a precursor.